Abstract
| Original language | English |
|---|---|
| Pages (from-to) | 3598-3615 |
| Number of pages | 18 |
| Journal | Circuits, Systems, and Signal Processing |
| Volume | 36 |
| Issue number | 9 |
| Early online date | 6 Jan 2017 |
| DOIs | |
| Publication status | Published - 1 Sep 2017 |
Fingerprint
Cite this
}
A Novel Low Delay High-Voltage Level Shifter with Transient Performance Insensitive to Parasitic Capacitance and Transfer Voltage Level. / Lai, Xinquan; Zhong, Longjie; Xu, Donglai; Wang, Hongyi; Yuan, Bing; Li, Qinqin; Ding, Rui; Zhao, Jingxiang.
In: Circuits, Systems, and Signal Processing, Vol. 36, No. 9, 01.09.2017, p. 3598-3615.Research output: Contribution to journal › Article
TY - JOUR
T1 - A Novel Low Delay High-Voltage Level Shifter with Transient Performance Insensitive to Parasitic Capacitance and Transfer Voltage Level
AU - Lai, Xinquan
AU - Zhong, Longjie
AU - Xu, Donglai
AU - Wang, Hongyi
AU - Yuan, Bing
AU - Li, Qinqin
AU - Ding, Rui
AU - Zhao, Jingxiang
PY - 2017/9/1
Y1 - 2017/9/1
N2 - In this paper, a new high-voltage level shifter (HVLS) structure is proposed, which has a significantly improved transient response over existing structures. To overcome signal transfer delay of the conventional HVLS caused by parasitic capacitance due to high-voltage MOSFETs, this structure employs a novel circuit module “inverse Schmitt trigger” to drive the pull-up transistors of conventional HVLS. As a result, the “Miller Plateau” caused by parasitic capacitance can be minimized. Hence, the overall transfer delay of the structure is significantly reduced. The simulation results based on SPECTRE and 0.5 μm high-voltage CMOS process show that compared to other currently available structures whose transfer delays are several nanoseconds on average, the proposed structure is able to provide a nanosecond transfer delay without using large boost capacitors which are impractical to be integrated or using complex logic units which decrease reliability of circuit. Also, the typical transfer delay of the proposed structure is a constant 1.3 ns, which is irrelevant to parasitic capacitance and insensitive to transfer voltage level.
AB - In this paper, a new high-voltage level shifter (HVLS) structure is proposed, which has a significantly improved transient response over existing structures. To overcome signal transfer delay of the conventional HVLS caused by parasitic capacitance due to high-voltage MOSFETs, this structure employs a novel circuit module “inverse Schmitt trigger” to drive the pull-up transistors of conventional HVLS. As a result, the “Miller Plateau” caused by parasitic capacitance can be minimized. Hence, the overall transfer delay of the structure is significantly reduced. The simulation results based on SPECTRE and 0.5 μm high-voltage CMOS process show that compared to other currently available structures whose transfer delays are several nanoseconds on average, the proposed structure is able to provide a nanosecond transfer delay without using large boost capacitors which are impractical to be integrated or using complex logic units which decrease reliability of circuit. Also, the typical transfer delay of the proposed structure is a constant 1.3 ns, which is irrelevant to parasitic capacitance and insensitive to transfer voltage level.
U2 - 10.1007/s00034-016-0488-z
DO - 10.1007/s00034-016-0488-z
M3 - Article
VL - 36
SP - 3598
EP - 3615
JO - Circuits, Systems, and Signal Processing
JF - Circuits, Systems, and Signal Processing
SN - 1531-5878
IS - 9
ER -