An Automatic Mapping from Statecharts to Verilog

Viet-Anh Vu Tran, Shengchao Qin, Wei-Ngan Chin

    Research output: Chapter in Book/Report/Conference proceedingConference contribution


    Statecharts is a visual formalism suitable for high-level system specification, while Verilog is a hardware description language that can be used for
    both behavioural and structural specification of (hardware) systems. This paper
    implements a semantics-preserving mapping from Graphical Statecharts to Verilog programs, which, to the best of our knowledge, is the first algorithm to bridge
    the gap between Statecharts and Verilog, and can be embedded into the hardware/software co-specification process [19] as a front-end.
    Original languageEnglish
    Title of host publicationTheoretical Aspects of Computing - ICTAC 2004
    EditorsZ. Liu , K. Araki
    PublisherSpringer Berlin
    ISBN (Electronic)9783540318620
    ISBN (Print)9783540253044
    Publication statusPublished - 2004
    EventTheoretical Aspects of Computing - ICTAC 2004, 1st International Colloquium - Guiyang, China
    Duration: 20 Sep 200424 Sep 2004
    Conference number: 1

    Publication series

    Name Lecture Notes in Computer Science
    PublisherSpringer Berlin


    ConferenceTheoretical Aspects of Computing - ICTAC 2004, 1st International Colloquium

    Fingerprint Dive into the research topics of 'An Automatic Mapping from Statecharts to Verilog'. Together they form a unique fingerprint.

    Cite this