An Automatic Mapping from Statecharts to Verilog

Viet-Anh Vu  Tran; Shengchao Qin; Wei-Ngan Chin

doi:10.1007/978-3-540-31862-0_15

An Automatic Mapping from Statecharts to Verilog

Viet-Anh Vu Tran, Shengchao Qin, Wei-Ngan Chin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Statecharts is a visual formalism suitable for high-level system specification, while Verilog is a hardware description language that can be used for
both behavioural and structural specification of (hardware) systems. This paper
implements a semantics-preserving mapping from Graphical Statecharts to Verilog programs, which, to the best of our knowledge, is the first algorithm to bridge
the gap between Statecharts and Verilog, and can be embedded into the hardware/software co-specification process [19] as a front-end.

Original language	English
Title of host publication	Theoretical Aspects of Computing - ICTAC 2004
Editors	Z. Liu , K. Araki
Publisher	Springer Berlin
Pages	187-203
Volume	3407
ISBN (Electronic)	9783540318620
ISBN (Print)	9783540253044
DOIs	https://doi.org/10.1007/978-3-540-31862-0_15
Publication status	Published - 2004
Event	Theoretical Aspects of Computing - ICTAC 2004, 1st International Colloquium - Guiyang, China Duration: 20 Sept 2004 → 24 Sept 2004 Conference number: 1

Publication series

Name	Lecture Notes in Computer Science
Publisher	Springer Berlin
Volume	3407

Conference

Conference	Theoretical Aspects of Computing - ICTAC 2004, 1st International Colloquium
Country/Territory	China
City	Guiyang
Period	20/09/04 → 24/09/04

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10.1007/978-3-540-31862-0_15

Cite this

@inproceedings{e977c78a7e6541eaaa7344fe1f978ca8,

title = "An Automatic Mapping from Statecharts to Verilog",

abstract = "Statecharts is a visual formalism suitable for high-level system specification, while Verilog is a hardware description language that can be used forboth behavioural and structural specification of (hardware) systems. This paperimplements a semantics-preserving mapping from Graphical Statecharts to Verilog programs, which, to the best of our knowledge, is the first algorithm to bridgethe gap between Statecharts and Verilog, and can be embedded into the hardware/software co-specification process [19] as a front-end.",

author = "Tran, {Viet-Anh Vu} and Shengchao Qin and Wei-Ngan Chin",

year = "2004",

doi = "10.1007/978-3-540-31862-0_15",

language = "English",

isbn = "9783540253044",

volume = "3407",

series = " Lecture Notes in Computer Science",

publisher = "Springer Berlin",

pages = "187--203",

editor = "{Liu }, Z. and {Araki }, K.",

booktitle = "Theoretical Aspects of Computing - ICTAC 2004",

address = "Germany",

note = "Theoretical Aspects of Computing - ICTAC 2004, 1st International Colloquium ; Conference date: 20-09-2004 Through 24-09-2004",

}

Tran, V-AV, Qin, S & Chin, W-N 2004, An Automatic Mapping from Statecharts to Verilog. in Z Liu & K Araki (eds), Theoretical Aspects of Computing - ICTAC 2004. vol. 3407, Lecture Notes in Computer Science, vol. 3407, Springer Berlin, pp. 187-203, Theoretical Aspects of Computing - ICTAC 2004, 1st International Colloquium, Guiyang, China, 20/09/04. https://doi.org/10.1007/978-3-540-31862-0_15

TY - GEN

T1 - An Automatic Mapping from Statecharts to Verilog

AU - Tran, Viet-Anh Vu

AU - Qin, Shengchao

AU - Chin, Wei-Ngan

N1 - Conference code: 1

PY - 2004

Y1 - 2004

N2 - Statecharts is a visual formalism suitable for high-level system specification, while Verilog is a hardware description language that can be used forboth behavioural and structural specification of (hardware) systems. This paperimplements a semantics-preserving mapping from Graphical Statecharts to Verilog programs, which, to the best of our knowledge, is the first algorithm to bridgethe gap between Statecharts and Verilog, and can be embedded into the hardware/software co-specification process [19] as a front-end.

AB - Statecharts is a visual formalism suitable for high-level system specification, while Verilog is a hardware description language that can be used forboth behavioural and structural specification of (hardware) systems. This paperimplements a semantics-preserving mapping from Graphical Statecharts to Verilog programs, which, to the best of our knowledge, is the first algorithm to bridgethe gap between Statecharts and Verilog, and can be embedded into the hardware/software co-specification process [19] as a front-end.

UR - http://dx.doi.org/10.1007/978-3-540-31862-0_15

U2 - 10.1007/978-3-540-31862-0_15

DO - 10.1007/978-3-540-31862-0_15

M3 - Conference contribution

SN - 9783540253044

VL - 3407

T3 - Lecture Notes in Computer Science

SP - 187

EP - 203

BT - Theoretical Aspects of Computing - ICTAC 2004

A2 - Liu , Z.

A2 - Araki , K.

PB - Springer Berlin

T2 - Theoretical Aspects of Computing - ICTAC 2004, 1st International Colloquium

Y2 - 20 September 2004 through 24 September 2004

ER -

An Automatic Mapping from Statecharts to Verilog

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