An improved parallel architecture for MPEG-4 motion estimation in 3G mobile applications

Donglai Xu, Rui Gao, Hadj Batatia

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Abstract

A high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low memory bandwidth and low clock rate requirements, thus primarily aiming at 3G mobile applications. Based on a one-dimensional tree architecture, the architecture employs the dual-register/buffer technique to reduce the preload and alignment cycles. As an example, full-search block matching algorithm has been mapped onto this architecture using a 16-PE array that has the ability to calculate the motion vectors of QCIF video sequences in real time at 1 MHz clock rate and using 15.5 Mbytes/s memory bandwidth.
Original languageEnglish
Title of host publicationProceedings of the International Conference on Multimedia and Expo
Pages441-444
Volume3
DOIs
Publication statusPublished - 2003
Event2003 International Conference on Multimedia and Expo. - Baltimore, United States
Duration: 6 Jul 20039 Jul 2003

Conference

Conference2003 International Conference on Multimedia and Expo.
Abbreviated titleICME '03
CountryUnited States
CityBaltimore
Period6/07/039/07/03
OtherProceedings (Cat. No.03TH8698)

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    Xu, D., Gao, R., & Batatia, H. (2003). An improved parallel architecture for MPEG-4 motion estimation in 3G mobile applications. In Proceedings of the International Conference on Multimedia and Expo (Vol. 3, pp. 441-444) https://doi.org/10.1109/ICME.2003.1221343