An improved parallel architecture for MPEG-4 motion estimation in 3G mobile applications

Donglai  Xu; Rui  Gao; Hadj Batatia

doi:10.1109/ICME.2003.1221343

An improved parallel architecture for MPEG-4 motion estimation in 3G mobile applications

Donglai Xu, Rui Gao, Hadj Batatia

SCEDT Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Abstract

A high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low memory bandwidth and low clock rate requirements, thus primarily aiming at 3G mobile applications. Based on a one-dimensional tree architecture, the architecture employs the dual-register/buffer technique to reduce the preload and alignment cycles. As an example, full-search block matching algorithm has been mapped onto this architecture using a 16-PE array that has the ability to calculate the motion vectors of QCIF video sequences in real time at 1 MHz clock rate and using 15.5 Mbytes/s memory bandwidth.

Original language	English
Title of host publication	Proceedings of the International Conference on Multimedia and Expo
Pages	441-444
Volume	3
DOIs	https://doi.org/10.1109/ICME.2003.1221343
Publication status	Published - 2003
Event	2003 International Conference on Multimedia and Expo. - Baltimore, United States Duration: 6 Jul 2003 → 9 Jul 2003

Conference

Conference	2003 International Conference on Multimedia and Expo.
Abbreviated title	ICME '03
Country/Territory	United States
City	Baltimore
Period	6/07/03 → 9/07/03
Other	Proceedings (Cat. No.03TH8698)

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10.1109/ICME.2003.1221343

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Cite this

@inproceedings{3bb37d03cb1e4865ba2a9c7f37b0cdb0,

title = "An improved parallel architecture for MPEG-4 motion estimation in 3G mobile applications",

abstract = "A high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low memory bandwidth and low clock rate requirements, thus primarily aiming at 3G mobile applications. Based on a one-dimensional tree architecture, the architecture employs the dual-register/buffer technique to reduce the preload and alignment cycles. As an example, full-search block matching algorithm has been mapped onto this architecture using a 16-PE array that has the ability to calculate the motion vectors of QCIF video sequences in real time at 1 MHz clock rate and using 15.5 Mbytes/s memory bandwidth.",

author = "Donglai Xu and Rui Gao and Hadj Batatia",

note = "Author can archive publisher's version/PDF. ; 2003 International Conference on Multimedia and Expo., ICME '03 ; Conference date: 06-07-2003 Through 09-07-2003",

year = "2003",

doi = "10.1109/ICME.2003.1221343",

language = "English",

volume = "3",

pages = "441--444",

booktitle = "Proceedings of the International Conference on Multimedia and Expo",

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AU - Xu, Donglai

AU - Gao, Rui

AU - Batatia, Hadj

N1 - Author can archive publisher's version/PDF.

PY - 2003

Y1 - 2003

N2 - A high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low memory bandwidth and low clock rate requirements, thus primarily aiming at 3G mobile applications. Based on a one-dimensional tree architecture, the architecture employs the dual-register/buffer technique to reduce the preload and alignment cycles. As an example, full-search block matching algorithm has been mapped onto this architecture using a 16-PE array that has the ability to calculate the motion vectors of QCIF video sequences in real time at 1 MHz clock rate and using 15.5 Mbytes/s memory bandwidth.

AB - A high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low memory bandwidth and low clock rate requirements, thus primarily aiming at 3G mobile applications. Based on a one-dimensional tree architecture, the architecture employs the dual-register/buffer technique to reduce the preload and alignment cycles. As an example, full-search block matching algorithm has been mapped onto this architecture using a 16-PE array that has the ability to calculate the motion vectors of QCIF video sequences in real time at 1 MHz clock rate and using 15.5 Mbytes/s memory bandwidth.

U2 - 10.1109/ICME.2003.1221343

DO - 10.1109/ICME.2003.1221343

M3 - Conference contribution

VL - 3

SP - 441

EP - 444

BT - Proceedings of the International Conference on Multimedia and Expo

T2 - 2003 International Conference on Multimedia and Expo.

Y2 - 6 July 2003 through 9 July 2003

ER -

An improved parallel architecture for MPEG-4 motion estimation in 3G mobile applications

Abstract

Conference

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