A high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low memory bandwidth and low clock rate requirements, thus primarily aiming at 3G mobile applications. Based on a one-dimensional tree architecture, the architecture employs the dual-register/buffer technique to reduce the preload and alignment cycles. As an example, full-search block matching algorithm has been mapped onto this architecture using a 16-PE array that has the ability to calculate the motion vectors of QCIF video sequences in real time at 1 MHz clock rate and using 15.5 Mbytes/s memory bandwidth.
|Title of host publication||Proceedings of the International Conference on Multimedia and Expo|
|Publication status||Published - 2003|
|Event||2003 International Conference on Multimedia and Expo. - Baltimore, United States|
Duration: 6 Jul 2003 → 9 Jul 2003
|Conference||2003 International Conference on Multimedia and Expo.|
|Abbreviated title||ICME '03|
|Period||6/07/03 → 9/07/03|
|Other||Proceedings (Cat. No.03TH8698)|
Bibliographical noteAuthor can archive publisher's version/PDF.
Xu, D., Gao, R., & Batatia, H. (2003). An improved parallel architecture for MPEG-4 motion estimation in 3G mobile applications. In Proceedings of the International Conference on Multimedia and Expo (Vol. 3, pp. 441-444) https://doi.org/10.1109/ICME.2003.1221343