Hardware/software partition is a critical phase in hardware/software co-design. This paper proposes a hybrid partitioning framework, in which we design a set of protocol converters to construct the interface component between the hardware and software components, and reuse the formerly well-built partitioning rules by introducing protocol converters and rewriting them for this hybrid framework. The hardware components generated by our partitioning process are coded directly in Verilog HDL, which will greatly facilitate the further compilation from it down to netlists.
|Title of host publication||Second Asia-Pacific conference on quality software, Proceedings|
|Publication status||Published - 2001|
|Event||2nd Asia-Pacific Conference on Quality Software - , Hong Kong|
Duration: 10 Dec 2001 → 11 Dec 2001
|Conference||2nd Asia-Pacific Conference on Quality Software|
|Period||10/12/01 → 11/12/01|