Employing integrated logic analysers and virtual I/Os to verify soft core protocol implementations

This paper will discuss the use of Integrated Logic analysers (ILAs) and Virtual I/Os (VIOs) to verify the behavior of soft core protocol implementations. In particular, a soft core implementation of the Controller Area Network (CAN) protocol will be used as a representative example to discuss the use of the proposed scheme. The paper will describe a procedure such that VIO and ILA may be employed to conduct lowcost conformance testing against specific test plans, both for the generation of test patterns and the verification of the resulting implementation behavior. As will be shown, VIOs are particularly helpful in generating highfrequency bit patterns, and may be used to great effect as a flexible bench pattern generator; the generated patterns make use the same system clock as the unit under test, and thus allow for tighter control of timing and more precise pattern generation. When coupled with suitable ILAs, such as the simple analysis tool Chipscope, it will be argued that such a scheme allows for a highly flexible and lowcost approach to protocol verification. Finally, we describe the use of a test bed in the verification of an opensource CAN soft core implementation against the relevant ISO testing standards.