Hardware/Software Partitioning in Verilog

Shengchao Qin, Jifeng He, Zongyan Qiu, Naixiao Zhang

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    We propose in this paper an algebraic approach to hardware/software partitioning in Verilog HDL. We explore a collection of algebraic laws for Verilog programs, from which we design a set of syntax-based algebraic rules to conduct hardware/software partitioning. The co-specification language and the target hardware and software description languages are specific subsets of Verilog, which brings forth our successful verification for the correctness of the partitioning process by algebra of Verilog. Facilitated by Verilog’s rich features, we have also successfully studied hw/sw partitioning for environment-driven systems.
    Original languageEnglish
    Title of host publicationFormal Methods and Software Engineering. ICFEM 2002
    EditorsC. George, H. Miao
    PublisherSpringer Berlin
    Pages168-179
    ISBN (Electronic)9783540361039
    ISBN (Print)9783540000297
    DOIs
    Publication statusPublished - 10 Oct 2002
    EventFormal Methods and Software Engineering, 4th International Conference on Formal Engineering Methods - Shanghai, China
    Duration: 21 Oct 200225 Oct 2002
    Conference number: 4

    Publication series

    NameLecture Notes in Computer Science
    PublisherSpringer, Berlin
    Volume2495

    Conference

    ConferenceFormal Methods and Software Engineering, 4th International Conference on Formal Engineering Methods
    Abbreviated titleICFEM 2002
    CountryChina
    CityShanghai
    Period21/10/0225/10/02

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