Hardware/Software Partitioning in Verilog

Shengchao Qin; Jifeng He; Zongyan Qiu; Naixiao   Zhang

doi:10.1007/3-540-36103-0_19

Hardware/Software Partitioning in Verilog

Shengchao Qin, Jifeng He, Zongyan Qiu, Naixiao Zhang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We propose in this paper an algebraic approach to hardware/software partitioning in Verilog HDL. We explore a collection of algebraic laws for Verilog programs, from which we design a set of syntax-based algebraic rules to conduct hardware/software partitioning. The co-specification language and the target hardware and software description languages are specific subsets of Verilog, which brings forth our successful verification for the correctness of the partitioning process by algebra of Verilog. Facilitated by Verilog’s rich features, we have also successfully studied hw/sw partitioning for environment-driven systems.

Original language	English
Title of host publication	Formal Methods and Software Engineering. ICFEM 2002
Editors	C. George, H. Miao
Publisher	Springer Berlin
Pages	168-179
ISBN (Electronic)	9783540361039
ISBN (Print)	9783540000297
DOIs	https://doi.org/10.1007/3-540-36103-0_19
Publication status	Published - 10 Oct 2002
Event	Formal Methods and Software Engineering, 4th International Conference on Formal Engineering Methods - Shanghai, China Duration: 21 Oct 2002 → 25 Oct 2002 Conference number: 4

Publication series

Name	Lecture Notes in Computer Science
Publisher	Springer, Berlin
Volume	2495

Conference

Conference	Formal Methods and Software Engineering, 4th International Conference on Formal Engineering Methods
Abbreviated title	ICFEM 2002
Country/Territory	China
City	Shanghai
Period	21/10/02 → 25/10/02

Access to Document

10.1007/3-540-36103-0_19

Cite this

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title = "Hardware/Software Partitioning in Verilog",

abstract = "We propose in this paper an algebraic approach to hardware/software partitioning in Verilog HDL. We explore a collection of algebraic laws for Verilog programs, from which we design a set of syntax-based algebraic rules to conduct hardware/software partitioning. The co-specification language and the target hardware and software description languages are specific subsets of Verilog, which brings forth our successful verification for the correctness of the partitioning process by algebra of Verilog. Facilitated by Verilog{\textquoteright}s rich features, we have also successfully studied hw/sw partitioning for environment-driven systems.",

author = "Shengchao Qin and Jifeng He and Zongyan Qiu and Naixiao Zhang",

year = "2002",

month = oct,

day = "10",

doi = "10.1007/3-540-36103-0_19",

language = "English",

isbn = "9783540000297",

series = "Lecture Notes in Computer Science",

publisher = "Springer Berlin",

pages = "168--179",

editor = "C. George and H. Miao",

booktitle = "Formal Methods and Software Engineering. ICFEM 2002",

address = "Germany",

note = "Formal Methods and Software Engineering, 4th International Conference on Formal Engineering Methods, ICFEM 2002 ; Conference date: 21-10-2002 Through 25-10-2002",

}

Qin, S, He, J, Qiu, Z & Zhang, N 2002, Hardware/Software Partitioning in Verilog. in C George & H Miao (eds), Formal Methods and Software Engineering. ICFEM 2002. Lecture Notes in Computer Science, vol. 2495, Springer Berlin, pp. 168-179, Formal Methods and Software Engineering, 4th International Conference on Formal Engineering Methods, Shanghai, China, 21/10/02. https://doi.org/10.1007/3-540-36103-0_19

TY - GEN

T1 - Hardware/Software Partitioning in Verilog

AU - Qin, Shengchao

AU - He, Jifeng

AU - Qiu, Zongyan

AU - Zhang, Naixiao

N1 - Conference code: 4

PY - 2002/10/10

Y1 - 2002/10/10

N2 - We propose in this paper an algebraic approach to hardware/software partitioning in Verilog HDL. We explore a collection of algebraic laws for Verilog programs, from which we design a set of syntax-based algebraic rules to conduct hardware/software partitioning. The co-specification language and the target hardware and software description languages are specific subsets of Verilog, which brings forth our successful verification for the correctness of the partitioning process by algebra of Verilog. Facilitated by Verilog’s rich features, we have also successfully studied hw/sw partitioning for environment-driven systems.

AB - We propose in this paper an algebraic approach to hardware/software partitioning in Verilog HDL. We explore a collection of algebraic laws for Verilog programs, from which we design a set of syntax-based algebraic rules to conduct hardware/software partitioning. The co-specification language and the target hardware and software description languages are specific subsets of Verilog, which brings forth our successful verification for the correctness of the partitioning process by algebra of Verilog. Facilitated by Verilog’s rich features, we have also successfully studied hw/sw partitioning for environment-driven systems.

UR - http://dx.doi.org/10.1007/3-540-36103-0_19

U2 - 10.1007/3-540-36103-0_19

DO - 10.1007/3-540-36103-0_19

M3 - Conference contribution

SN - 9783540000297

T3 - Lecture Notes in Computer Science

SP - 168

EP - 179

BT - Formal Methods and Software Engineering. ICFEM 2002

A2 - George, C.

A2 - Miao, H.

PB - Springer Berlin

T2 - Formal Methods and Software Engineering, 4th International Conference on Formal Engineering Methods

Y2 - 21 October 2002 through 25 October 2002

ER -

Hardware/Software Partitioning in Verilog

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