Mapping Statecharts to Verilog for Hardware/Software Co-specification

Shengchao Qin; Wei-Ngan Chin

doi:10.1007/978-3-540-45236-2_17

Mapping Statecharts to Verilog for Hardware/Software Co-specification

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Hardware-Software co-specification is a critical phase in co-design. Our co-specification process starts with a high level graphical description in Statecharts and ends with an equivalent parallel composition of hardware and software descriptions in Verilog. In this paper, we investigate the Statecharts formalism by providing it a formal syntax and a compositional operational semantics. After that, we design a semantics-preserving mapping function to transform a Statecharts description into Verilog specification. We can combine this mapping with our previous formal partitioning process so as to form a more complete and automated co-specification process.

Original language	English
Title of host publication	FME 2003: Formal Methods
Publisher	Springer Berlin
Pages	282-300
ISBN (Electronic)	9783540452362
ISBN (Print)	9783540408284
DOIs	https://doi.org/10.1007/978-3-540-45236-2_17
Publication status	Published - 2003
Event	FME 2003: Formal Methods: International Symposium of Formal Methods Europe - Piza, Italy Duration: 8 Sept 2003 → 14 Sept 2003

Conference

Conference	FME 2003: Formal Methods
Country/Territory	Italy
City	Piza
Period	8/09/03 → 14/09/03

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10.1007/978-3-540-45236-2_17

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title = "Mapping Statecharts to Verilog for Hardware/Software Co-specification",

abstract = "Hardware-Software co-specification is a critical phase in co-design. Our co-specification process starts with a high level graphical description in Statecharts and ends with an equivalent parallel composition of hardware and software descriptions in Verilog. In this paper, we investigate the Statecharts formalism by providing it a formal syntax and a compositional operational semantics. After that, we design a semantics-preserving mapping function to transform a Statecharts description into Verilog specification. We can combine this mapping with our previous formal partitioning process so as to form a more complete and automated co-specification process.",

author = "Shengchao Qin and Wei-Ngan Chin",

year = "2003",

doi = "10.1007/978-3-540-45236-2_17",

language = "English",

isbn = "9783540408284",

pages = "282--300",

booktitle = "FME 2003: Formal Methods",

publisher = "Springer Berlin",

address = "Germany",

note = "FME 2003: Formal Methods : International Symposium of Formal Methods Europe ; Conference date: 08-09-2003 Through 14-09-2003",

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T1 - Mapping Statecharts to Verilog for Hardware/Software Co-specification

AU - Qin, Shengchao

AU - Chin, Wei-Ngan

PY - 2003

Y1 - 2003

N2 - Hardware-Software co-specification is a critical phase in co-design. Our co-specification process starts with a high level graphical description in Statecharts and ends with an equivalent parallel composition of hardware and software descriptions in Verilog. In this paper, we investigate the Statecharts formalism by providing it a formal syntax and a compositional operational semantics. After that, we design a semantics-preserving mapping function to transform a Statecharts description into Verilog specification. We can combine this mapping with our previous formal partitioning process so as to form a more complete and automated co-specification process.

AB - Hardware-Software co-specification is a critical phase in co-design. Our co-specification process starts with a high level graphical description in Statecharts and ends with an equivalent parallel composition of hardware and software descriptions in Verilog. In this paper, we investigate the Statecharts formalism by providing it a formal syntax and a compositional operational semantics. After that, we design a semantics-preserving mapping function to transform a Statecharts description into Verilog specification. We can combine this mapping with our previous formal partitioning process so as to form a more complete and automated co-specification process.

UR - http://dx.doi.org/10.1007/978-3-540-45236-2_17

U2 - 10.1007/978-3-540-45236-2_17

DO - 10.1007/978-3-540-45236-2_17

M3 - Conference contribution

SN - 9783540408284

SP - 282

EP - 300

BT - FME 2003: Formal Methods

PB - Springer Berlin

T2 - FME 2003: Formal Methods

Y2 - 8 September 2003 through 14 September 2003

ER -

Mapping Statecharts to Verilog for Hardware/Software Co-specification

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