Hardware-Software co-specification is a critical phase in co-design. Our co-specification process starts with a high level graphical description in Statecharts and ends with an equivalent parallel composition of hardware and software descriptions in Verilog. In this paper, we investigate the Statecharts formalism by providing it a formal syntax and a compositional operational semantics. After that, we design a semantics-preserving mapping function to transform a Statecharts description into Verilog specification. We can combine this mapping with our previous formal partitioning process so as to form a more complete and automated co-specification process.
|Title of host publication||FME 2003: Formal Methods|
|Publication status||Published - 2003|
|Event||FME 2003: Formal Methods: International Symposium of Formal Methods Europe - Piza, Italy|
Duration: 8 Sep 2003 → 14 Sep 2003
|Conference||FME 2003: Formal Methods|
|Period||8/09/03 → 14/09/03|