Mapping Statecharts to Verilog for Hardware/Software Co-specification

Shengchao Qin, Wei-Ngan Chin

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    Hardware-Software co-specification is a critical phase in co-design. Our co-specification process starts with a high level graphical description in Statecharts and ends with an equivalent parallel composition of hardware and software descriptions in Verilog. In this paper, we investigate the Statecharts formalism by providing it a formal syntax and a compositional operational semantics. After that, we design a semantics-preserving mapping function to transform a Statecharts description into Verilog specification. We can combine this mapping with our previous formal partitioning process so as to form a more complete and automated co-specification process.
    Original languageEnglish
    Title of host publicationFME 2003: Formal Methods
    PublisherSpringer Berlin
    Pages282-300
    ISBN (Electronic)9783540452362
    ISBN (Print)9783540408284
    DOIs
    Publication statusPublished - 2003
    EventFME 2003: Formal Methods: International Symposium of Formal Methods Europe - Piza, Italy
    Duration: 8 Sep 200314 Sep 2003

    Conference

    ConferenceFME 2003: Formal Methods
    CountryItaly
    CityPiza
    Period8/09/0314/09/03

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