TY - JOUR
T1 - Oversampling Successive Approximation Technique for MEMS Differential Capacitive Sensor
AU - Zhong, Longjie
AU - Lai, Xinquan
AU - Xu, Donglai
N1 - Author can archive post-print (ie final draft post-refereeing). For full details see http://www.sherpa.ac.uk/romeo/issn/0018-9200/ [Accessed: 27/07/2018]
PY - 2018/8/1
Y1 - 2018/8/1
N2 - This paper proposed an over sampling successive approximation (OSSA) technique to build switched-capacitor capacitance-to-voltage convertor (SC-CVC) for readout circuit of MEMS differential capacitive sensor. The readout circuit employing the OSSA technique has significantly improved resistance to common-mode parasitic capacitance of the input terminal of the readout circuit. In the OSSA readout circuit, there are 5 main non-ideal characteristics: holding error, recovery degradation, increment degradation, rise-edge degradation and charge injection which reduce the accuracy and the settling time of the circuit. These problems are explained in detail and their solutions are given in the paper. The OSSA readout circuit is fabricated in a commercial 0.18um BCD process. To show the improvement evidently, a reported traditional readout circuit is also reproduced and fabricated using the same process. Compared with the traditional readout circuit, the proposed readout circuit reduces the affect of common-mode parasitic capacitance on the accuracy of SC-CVC by more than 23.8 dB, reduces power dissipation by 69.3%, and reduces die area by 50%.
AB - This paper proposed an over sampling successive approximation (OSSA) technique to build switched-capacitor capacitance-to-voltage convertor (SC-CVC) for readout circuit of MEMS differential capacitive sensor. The readout circuit employing the OSSA technique has significantly improved resistance to common-mode parasitic capacitance of the input terminal of the readout circuit. In the OSSA readout circuit, there are 5 main non-ideal characteristics: holding error, recovery degradation, increment degradation, rise-edge degradation and charge injection which reduce the accuracy and the settling time of the circuit. These problems are explained in detail and their solutions are given in the paper. The OSSA readout circuit is fabricated in a commercial 0.18um BCD process. To show the improvement evidently, a reported traditional readout circuit is also reproduced and fabricated using the same process. Compared with the traditional readout circuit, the proposed readout circuit reduces the affect of common-mode parasitic capacitance on the accuracy of SC-CVC by more than 23.8 dB, reduces power dissipation by 69.3%, and reduces die area by 50%.
UR - http://www.scopus.com/inward/record.url?scp=85046827525&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2018.2827922
DO - 10.1109/JSSC.2018.2827922
M3 - Article
SN - 0018-9200
VL - 53
SP - 2240
EP - 2251
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 8
ER -