TY - JOUR
T1 - Precision Improvement of Power-Efficient Capacitive Senor Readout Circuit Using Multi-Nested Clocks
AU - Zhong, Longjie
AU - Xu, Donglai
AU - Lai, Xinquan
AU - Wang, Yuheng
AU - Liao, Xinqin
AU - Fang, Zhongyuan
AU - Zheng, Yuanjin
PY - 2020/8/1
Y1 - 2020/8/1
N2 - This paper proposes a clock strategy to improve the precision of power-efficient readout circuit for capacitive sensor. To achieve high power efficiency, capacitive sensor such as MEMS accelerometer is designed with open-loop architecture rather than close-loop one. In the open-loop architecture, the capacitance variation of sensing element is limited to femto-farad level in order to overcome nonlinearity problem. However, due to this limitation, the signal charge from sensing element is weak and the interference charge due to coupling capacitance between clock wires and sensing electrodes becomes a significant issue. Therefore, split clock bus is employed to meet this challenge, but the split clock bus introduces the timing mismatch which causes the charge injection sensitive to fabrication process and circuit operating voltage. As a result, the input offset, the variation of the offset and the nonlinearity of readout circuit will increase, and this will lead to reduction of precision. In this work, a clock scheme named ``multi-nested clocks'' is proposed to address the charge injection problem. The multi-nested clocks are demonstrated in a readout circuit fabricated using a 0.18-μ m BCD process. The measurement results show that compared to the readout circuit using traditional clock, the readout circuit using the multi-nested clocks significantly reduces the equivalent input offset from 1.66fF to 0.25fF, the offset variation from 1.4fF to 0.2fF and the nonlinearity from 5.5% to 0.9%.
AB - This paper proposes a clock strategy to improve the precision of power-efficient readout circuit for capacitive sensor. To achieve high power efficiency, capacitive sensor such as MEMS accelerometer is designed with open-loop architecture rather than close-loop one. In the open-loop architecture, the capacitance variation of sensing element is limited to femto-farad level in order to overcome nonlinearity problem. However, due to this limitation, the signal charge from sensing element is weak and the interference charge due to coupling capacitance between clock wires and sensing electrodes becomes a significant issue. Therefore, split clock bus is employed to meet this challenge, but the split clock bus introduces the timing mismatch which causes the charge injection sensitive to fabrication process and circuit operating voltage. As a result, the input offset, the variation of the offset and the nonlinearity of readout circuit will increase, and this will lead to reduction of precision. In this work, a clock scheme named ``multi-nested clocks'' is proposed to address the charge injection problem. The multi-nested clocks are demonstrated in a readout circuit fabricated using a 0.18-μ m BCD process. The measurement results show that compared to the readout circuit using traditional clock, the readout circuit using the multi-nested clocks significantly reduces the equivalent input offset from 1.66fF to 0.25fF, the offset variation from 1.4fF to 0.2fF and the nonlinearity from 5.5% to 0.9%.
U2 - 10.1109/TCSI.2020.2979316
DO - 10.1109/TCSI.2020.2979316
M3 - Article
VL - 67
SP - 2578
EP - 2587
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
SN - 1549-8328
IS - 8
ER -