In this paper the timing properties of a single switch LAN are analyzed. The analysis is based upon relatively simple iterative algorithms to analyze the duration of the synchronous busy period of a message set, assuming FIFO buffering in both the source nodes and switch are employed. In this paper, the real-time traffic (periodic and sporadic) is also assumed to be subject to random interference from other sources, and a probabilistic stance is taken. A number of observations are made based upon our initial analysis and investigations, and preliminary algorithms are proposed to probabilistically estimate the worst case queuing delays at source nodes and switch output ports assuming some knowledge of the (mean) interference levels are known. The work was principally motivated by the need for easy-to-apply and relatively accurate probabilistic timing analysis in distributed automation implementations; it may also be applicable to other industrial contexts. The paper concludes that the techniques may be able to provide a useful building block for larger packet switched networks with deterministic and stochastic traffic sources, and future work will consider extensions to multiple switch hierarchical networks.
|Number of pages||8|
|Journal||Current Analysis on Communication Engineering|
|Publication status||Published - 8 Oct 2018|