Realizing Live Sequence Charts in SystemVerilog

Hai H. Wang, Shengchao Qin, Jun Sun, Jin Song Dong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Abstract

The design of an embedded control system starts with an investigation of properties and behaviors of the process evolving within its environment, and an analysis of the requirement for its safety performance. In early stages, system requirements are often specified as scenarios of behaviour using sequence charts for different use cases. This specification must be precise, intuitive and expressive enough to capture different aspects of embedded control systems. As a rather rich and useful extension to the classical message sequence charts, Live Sequence Charts (LSC), which provide a rich collection of constructs for specifying both possible and mandatory behaviors, are very suitable for designing an embedded control system. However, it is not a trivial task to realize a high-level design model in executable program codes effectively and correctly. This paper tackles the challenging task by providing a mapping algorithm to automatically synthesize SystemVerilog programs from given LSC specifications.
Original languageEnglish
Title of host publicationTASE 2007: First joint IEEE/IFIP symposium on theoretical aspects of software engineering, proceedings
Pages379-388
DOIs
Publication statusPublished - 2007
Event1st Joint IEEE/IFIP Symposium on Theoretical Aspects of Software Engineering - Shanghai, China
Duration: 6 Jun 20078 Jun 2007

Conference

Conference1st Joint IEEE/IFIP Symposium on Theoretical Aspects of Software Engineering
Abbreviated titleTASE'07
CountryChina
CityShanghai
Period6/06/078/06/07

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    Wang, H. H., Qin, S., Sun, J., & Dong, J. S. (2007). Realizing Live Sequence Charts in SystemVerilog. In TASE 2007: First joint IEEE/IFIP symposium on theoretical aspects of software engineering, proceedings (pp. 379-388) https://doi.org/10.1109/TASE.2007.41