Reconfigurable hardware implementation of an improved parallel architecture for MPEG-4 motion estimation in mobile applications

A reconfigurable hardware implementation of a high-parallel architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low power dissipation and low cost, thus primarily aiming at video-based mobile applications. The architecture employs a dual-register/buffer technique to reduce preload and alignment cycles and a high-parallel pipeline to reduce power consumption of redundant memory access. As an example, a content-based full-search blockmatching algorithm has been mapped onto this architecture using a 16-PE array. This has the ability to calculate the motion vectors of 20fps QCIF video sequences in real time at 8.2 MHz clock rate with 36.76mw power dissipation using a Xilinx Spartan II FPGA.