Thermal effects of die-attach voids location and style on performance of chip level package

K. C. Otiaba, R. S. Bhatti, N. N. Ekere, S. Mallik, E. H. Amalu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Thermal characterisation of chip-scale packaged power devices is crucial to the development of advanced electronic packages for communication and automotive applications. Solder thermal interface materials (STIMs) are often employed in the packaging of power semiconductors to enhance heat dissipation from the chip to the heat spreader. However, voids formation in STIMs impedes heat flow and could result in increase in the chip peak temperature. Three-dimensional finite element analysis is employed to investigate the thermal effects of lead-free solder void percentages, locations and styles on packaged semiconductor device. The thermal resistance of each voiding case is calculated to evaluate the thermal response of the electronic package. The results show that the thermal resistance and peak temperature of electronic package can significantly increase depending on the percentage, location and style of voids. The results would assist packaging and design engineers in the characterisation of the thermal impacts of different solder void patterns.

Original languageEnglish
Title of host publication3rd IEEE International Conference on Adaptive Science and Technology, ICAST 2011, Proceedings
Pages231-236
Number of pages6
DOIs
Publication statusPublished - 1 Dec 2011
Event3rd IEEE International Conference on Adaptive Science and Technology - Abuja, Nigeria
Duration: 24 Nov 201126 Nov 2011

Conference

Conference3rd IEEE International Conference on Adaptive Science and Technology
Abbreviated titleICAST 2011
CountryNigeria
CityAbuja
Period24/11/1126/11/11

Fingerprint Dive into the research topics of 'Thermal effects of die-attach voids location and style on performance of chip level package'. Together they form a unique fingerprint.

  • Cite this

    Otiaba, K. C., Bhatti, R. S., Ekere, N. N., Mallik, S., & Amalu, E. H. (2011). Thermal effects of die-attach voids location and style on performance of chip level package. In 3rd IEEE International Conference on Adaptive Science and Technology, ICAST 2011, Proceedings (pp. 231-236). [6145176] https://doi.org/10.1109/ICASTech.2011.6145176