In this paper, we proposed a flexible VLSI-based parallel processing architecture for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms.
|Title of host publication||ICECS 2001|
|Subtitle of host publication||8th IEEE international conference on electronics, circuits and systems|
|Publication status||Published - 2001|
|Event||8th IEEE International Conference on Electronics, Circuits and Systems - St. Julians, Malta|
Duration: 2 Sep 2001 → 5 Sep 2001
Conference number: 8
|Conference||8th IEEE International Conference on Electronics, Circuits and Systems|
|Period||2/09/01 → 5/09/01|
Bibliographical noteAuthor can archive publisher's version/PDF.
Xu, D., & Bentley, J. (2001). VLSI-based parallel architecture for block-matching motion estimation in low bit-rate video coding. In ICECS 2001: 8th IEEE international conference on electronics, circuits and systems (Vol. I-III, pp. 217-220) https://doi.org/10.1109/ICECS.2001.957719