VLSI-based parallel architecture for block-matching motion estimation in low bit-rate video coding

Donglai Xu, John Bentley

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Abstract

In this paper, we proposed a flexible VLSI-based parallel processing architecture for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms.
Original languageEnglish
Title of host publicationICECS 2001
Subtitle of host publication8th IEEE international conference on electronics, circuits and systems
Pages217-220
VolumeI-III
DOIs
Publication statusPublished - 2001
Event8th IEEE International Conference on Electronics, Circuits and Systems - St. Julians, Malta
Duration: 2 Sep 20015 Sep 2001
Conference number: 8

Conference

Conference8th IEEE International Conference on Electronics, Circuits and Systems
CountryMalta
CitySt. Julians
Period2/09/015/09/01

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    Xu, D., & Bentley, J. (2001). VLSI-based parallel architecture for block-matching motion estimation in low bit-rate video coding. In ICECS 2001: 8th IEEE international conference on electronics, circuits and systems (Vol. I-III, pp. 217-220) https://doi.org/10.1109/ICECS.2001.957719