VLSI-based parallel architecture for block-matching motion estimation in low bit-rate video coding

Donglai Xu; John Bentley

doi:10.1109/ICECS.2001.957719

VLSI-based parallel architecture for block-matching motion estimation in low bit-rate video coding

Donglai Xu, John Bentley

SCEDT Engineering

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Abstract

In this paper, we proposed a flexible VLSI-based parallel processing architecture for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms.

Original language	English
Title of host publication	ICECS 2001
Subtitle of host publication	8th IEEE international conference on electronics, circuits and systems
Pages	217-220
Volume	I-III
DOIs	https://doi.org/10.1109/ICECS.2001.957719
Publication status	Published - 2001
Event	8th IEEE International Conference on Electronics, Circuits and Systems - St. Julians, Malta Duration: 2 Sept 2001 → 5 Sept 2001 Conference number: 8

Conference

Conference	8th IEEE International Conference on Electronics, Circuits and Systems
Country/Territory	Malta
City	St. Julians
Period	2/09/01 → 5/09/01

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10.1109/ICECS.2001.957719

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Cite this

@inproceedings{a57c995bfc57499dab6123131b5a2c34,

title = "VLSI-based parallel architecture for block-matching motion estimation in low bit-rate video coding",

abstract = "In this paper, we proposed a flexible VLSI-based parallel processing architecture for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms.",

author = "Donglai Xu and John Bentley",

note = "Author can archive publisher's version/PDF. ; 8th IEEE International Conference on Electronics, Circuits and Systems ; Conference date: 02-09-2001 Through 05-09-2001",

year = "2001",

doi = "10.1109/ICECS.2001.957719",

language = "English",

volume = "I-III",

pages = "217--220",

booktitle = "ICECS 2001",

}

Xu, D & Bentley, J 2001, VLSI-based parallel architecture for block-matching motion estimation in low bit-rate video coding. in ICECS 2001: 8th IEEE international conference on electronics, circuits and systems. vol. I-III, pp. 217-220, 8th IEEE International Conference on Electronics, Circuits and Systems, St. Julians, Malta, 2/09/01. https://doi.org/10.1109/ICECS.2001.957719

TY - GEN

T1 - VLSI-based parallel architecture for block-matching motion estimation in low bit-rate video coding

AU - Xu, Donglai

AU - Bentley, John

N1 - Conference code: 8

PY - 2001

Y1 - 2001

N2 - In this paper, we proposed a flexible VLSI-based parallel processing architecture for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms.

AB - In this paper, we proposed a flexible VLSI-based parallel processing architecture for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms.

U2 - 10.1109/ICECS.2001.957719

DO - 10.1109/ICECS.2001.957719

M3 - Conference contribution

VL - I-III

SP - 217

EP - 220

BT - ICECS 2001

T2 - 8th IEEE International Conference on Electronics, Circuits and Systems

Y2 - 2 September 2001 through 5 September 2001

ER -

VLSI-based parallel architecture for block-matching motion estimation in low bit-rate video coding

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